Semiconductor interconnect

ABSTRACT

One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

FIELD

The disclosure herein relates generally to semiconductor processing, andmore particularly to interconnect that provides a balance between goodperformance and small feature size.

BACKGROUND

Several trends presently exist in the semiconductor and electronicsindustry. Compared to prior generations of devices, modern devices aresmaller and operate at lower power and higher frequencies. One reasonfor these trends is that personal devices are being fabricated to berelatively small and portable, thereby relying on a battery as theirprimary power supply. For example, cellular phones, personal computingdevices, and personal sound systems are devices that are in great demandin the consumer market. In addition to being smaller and more portable,personal devices are also requiring increased memory and morecomputational power and speed. In light of these trends, there is anever increasing demand in the industry for smaller and fastertransistors used to provide the core functionality of the integratedcircuits (ICs) used in these devices. The main reason to reduce circuitarea is cost. Smaller die size implies more die on a wafer.Consequently, if everything else remains the same, the cost per die islower.

It can be appreciated that integrated circuits with more devices (i.e.,having higher densities) tend to provide more functionality thanintegrated circuits with fewer devices (i.e., having lower densities).Accordingly, in the semiconductor industry there is a continuing trendtoward manufacturing integrated circuits with higher densities. Toachieve high densities, there are on-going efforts toward scaling downdimensions (e.g., at submicron levels) on semiconductor wafers. In orderto accomplish such high densities, smaller feature sizes, smallerseparations between features, and more precise feature shapes arerequired in integrated circuits fabricated on small rectangular portionsof the wafer, commonly known as die.

Generally speaking, integrated circuit designers organize transistorsinto standard cell libraries, where each standard cell within thelibrary corresponds to a particular functional block. For example, onefunctional block could correspond to NOR functionality and anotherfunctional block could correspond to NAND functionality. Thesefunctional blocks provide designers with building blocks that they cantile together to achieve complex functionality. By re-engineering howfeatures are arranged in standard cell libraries, higher densities canbe achieved.

SUMMARY

The following presents a summary to provide a basic understanding of oneor more aspects of the disclosure herein. This summary is not anextensive overview. It is intended neither to identify key or criticalelements nor to delineate scope of the disclosure herein. Rather, itsprimary purpose is merely to present one or more aspects in a simplifiedform as a prelude to a more detailed description that is presentedlater.

One embodiment relates to an integrated circuit that includes at leastone semiconductor device. The integrated circuit includes a firstcontact associated with a first terminal of the semiconductor device.The first contact spans a dielectric layer and couples the firstterminal to an interconnect line that communicates signals horizontallyon the integrated circuit, where the interconnect line has a firstcomposition. The integrated circuit further includes a second contactassociated with a second terminal of the semiconductor device. Thesecond contact spans the dielectric layer and couples the secondterminal to a landing pad to which a via is coupled, where the landingpad has a second composition that differs from the first composition.

To the accomplishment of the foregoing and related ends, the followingdescription and annexed drawings set forth certain illustrative aspects.Other aspects, advantages and/or features may, however, become apparentfrom the following detailed description when considered in conjunctionwith the annexed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A-1B are cross-sectional views of a transistor with a copperlanding pad and copper interconnect line;

FIG. 2 is a cross-sectional view of a transistor that includes a landingpad with a relatively small area;

FIG. 3 is a flowchart that illustrates an embodiment of a method forforming semiconductor interconnect;

FIGS. 4-13 are cross-sectional views of a more detailed embodiment of amethod for forming semiconductor interconnect;

FIG. 14 is another flowchart that illustrates an embodiment of a methodfor forming semiconductor interconnect;

FIGS. 15-21 are cross-sectional views of a more detailed embodiment of amethod for forming semiconductor interconnect;

FIG. 22 is another flowchart that illustrates an embodiment of a methodfor forming semiconductor interconnect;

FIGS. 23-31 are cross-sectional views of a more detailed embodiment of amethod for forming semiconductor interconnect;

FIG. 32 is another flowchart that illustrates an embodiment of a methodfor forming semiconductor interconnect; and

FIGS. 33-43 are cross-sectional views of a more detailed embodiment of amethod for forming semiconductor interconnect.

DETAILED DESCRIPTION

The description herein is made with reference to the drawings, whereinlike reference numerals are generally utilized to refer to like elementsthroughout, and wherein the various structures are not necessarily drawnto scale. In the following description, for purposes of explanation,numerous specific details are set forth in order to facilitateunderstanding. It may be evident, however, to one skilled in the art,that one or more aspects described herein may be practiced with a lesserdegree of these specific details. In other instances, known structuresand devices are shown in block diagram form to facilitate understanding.

FIG. 1A illustrates a semiconductor device 100 in the form of a Metaloxide field effect transistor (MOSFET). The MOSFET is formed in asemiconductor body 102 and has several layers of interconnect 104fashioned thereover. The MOSFET includes several terminals to whichbiases can be selectively applied to operate the device. These terminalscould include a source 106 and a drain 108 that are formed in thesemiconductor body and are separated from one another by a channelregion 110 under a gate electrode 112. The gate electrode 112 and thebulk region of the MOSFET (e.g., n-well) could also constitute terminalsfor purposes of this disclosure. The illustrated MOSFET also includesspacers laterally flanking the gate electrode and a gate oxide thatseparates the gate electrode from the channel region.

A first contact 114 spans a dielectric layer 116 to connect the source106 to a metal1 interconnect line 118. The metal1 interconnect line 118,which is made of copper in one embodiment, typically carries signalsbetween devices that are in separate areas of the integrated circuit.Thus, it may be advantageous to make the interconnect line out of lowresistance material, such as copper, thereby limiting the resistance ofthe interconnect and potentially providing faster device switchingtimes.

A second contact 120 also spans the dielectric layer 116 to connect thedrain 108 to a metal1 landing pad 122. The landing pad 122 may differfrom the interconnect line 118 in that the landing pad typically doesnot carry signals horizontally between devices, but rather serves as avertical connection so the second contact 120 can be coupled to a via124. The via 124 may include a via top 126, which may be a landing padfor connecting to another via (not shown). Alternatively, the via top126 may be an interconnect line that carries signals horizontally toother devices (i.e., laterally between devices or into the plane of thepage between devices).

To limit the number of process steps and correspondingly limitmanufacturing costs, the landing pad 122 could be made of the samematerial as the interconnect line 118. As mentioned, copper is often thematerial of choice due to its low resistance. In state-of-the-arttechnologies the minimum area of a copper pad is not limited by thelithographic and etch process capabilities to form the small trenchwhich would be filled with copper but is limited by the ability to fillthe trench with copper without voids, however, due to the fact that thecopper electroplating process does not fill small openings particularlywell, as attempts are made to shrink the feature sizes, voids 128 mayappear during processing as shown in FIG. 1B. These voids may causefailures, thereby reducing manufacturing yields or may greatly reducereliability causing the circuit to fail when current flows through apartial void at a later time. Although FIG. 1B shows one type of void,it will be appreciated that FIG. 1B is only presented for purposes ofunderstanding and that other types of voids, such as keyhole voids,could remain after processing or could occur during subsequent use(e.g., due to electromigration).

FIG. 2 shows one example of a configuration 200 that can limit theformation of voids, while at the same time providing high-performance(low resistance) interconnect lines and providing a mechanism forscaling to smaller standard cells areas. To achieve this balance, thisconfiguration 200 includes a metal1 landing pad 202 that is formedcontinuously with its associated contact 204. In some embodiments, themetal1 landing pads 202 and the metal1 interconnect lines 206 may havedifferent compositions. In these and other embodiments, the metal1landing pads and metal1 interconnect lines could also have differentareas and/or widths.

Depending on the specific implantation, this configuration 200 couldprovide varying degrees of balance between good performance and smallarea. This balance may be achieved in part due to the fact that themetal1 landing pads 202 and metal1 interconnect lines 206 could havedifferent compositions. In some embodiments, for example, the metal1interconnect line 206 could be made of copper or some otherlow-resistance material. Therefore, the configuration 200 can providelow-resistance interconnect lines between devices. In addition, however,the landing pad 202 could be made out of a ductile material, such astungsten, which is deposited using a CVD process that can fill arelatively small area that electroplated copper would be unable to fill.Therefore, “voiding” can be eliminated and the area of the standard cellmay be further scaled beyond what has been possible with copper. Forexample, in FIG. 2's illustrated embodiment, Standard Cell N′ has“squeezed” width Δ from the Standard Cell N. This area reduction can besignificant when applied to an entire integrated chip, which couldinclude thousands or even millions of standard cells.

Even if the ductile material for the landing pad 202 has a relativelyhigh resistance, the degradation in switching time performance is oftenrelatively small because signals travel only vertically across thelanding pad 202 (i.e., from the contact 204 to the via 208, and viceversa). Thus, the landing pad 202 does not typically carry signals forlong distances between devices and therefore, the reduction in areaoutweighs the slight degradation due to any added resistance. Inembodiments where the metal1 interconnect lines 206 are still made ofcopper, fast switching times can still be achieved.

Thus, the inventors have appreciated that, by using different materialsto fill the trenches and the small landing pads, the area of the landingpad can be shrunk to correspond to the limits of state-of-the-artlithographic and etch processes without forming undesirable voids. Theinventors have also appreciated that the state-of-the-art depositionprocesses for conductive materials that are used to fill contact holes,(e.g., Ti/TiN/W), can also be used to fill the smallest landing padtrenches that can be patterned and etched. In addition, in someembodiments, the present invention may reduce contact resistance,especially in instances when the metal-1 trench and contact areas duenot coincide due to processing misalignment between adjacent layers. Theinvention also enables reduction of the minimum metal-1 enclosure forcontact design rules for the same reason.

Several illustrative examples of integrated circuits and manufacturingmethods are now set forth below. Some figures (FIG. 3, FIG. 14, FIG. 22,and FIG. 32) show methods as flowcharts, while other figures (FIGS.4-13, FIGS. 15-21, FIGS. 23-31, and FIGS. 33-43, respectively) showvarious cross sectional views that could correspond to the blocks of therespective flowcharts. Although these methods are illustrated anddescribed below as a series of acts or events, it will be appreciatedthat the present invention is not limited by the illustrated ordering ofsuch acts or events. For example, some acts may occur in differentorders and/or concurrently with other acts or events apart from thoseillustrated and/or described herein, in accordance with the invention.In addition, not all illustrated steps may be required to implement amethodology in accordance with the present invention. Furthermore, themethods according to the present invention may be implemented inassociation with the devices and systems illustrated and describedherein as well as in association with other structures not illustrated.

Referring now to FIG. 3 one can see a flowchart 300 for forming landingpads with a reduced width. Generally speaking, the flowchart illustratesblocks where alternating conducting and insulating layers are depositedover a semiconductor body to form interconnect. The features within thelayers are formed by patterning photoresist (resist) to expose someareas while masking off other areas. The exposed areas are then etchedaway and the patterned resist is then removed. Conductive features, suchas contacts and vias are then formed to make the interconnect. Chemicalmechanical polishing (CMP) is used to planarize the top surface of thestructure at various blocks in the process.

Referring now to FIGS. 4-13, one can see several cross-sectional viewsduring the manufacture of the device. These cross-sections are but oneexample of a method corresponding to the flowchart of FIG. 3, and otherexamples are also possible. For purposes of clarity and simplicity,these cross sectional views do not explicitly show all blocks of theflowchart. For example, patterned resist layers (masks) are not shown,nor are CMP blocks.

Referring now to FIG. 4, one can see a structure 400 in which first andsecond contact holes 402, 404 have been formed in the first dielectriclayer 406. For example, these contact holes 402, 404 could be formed byusing reactive ion etching (RIE).

In FIG. 5, a landing pad recess 500 has been formed near the top of thesecond contact hole. To form this recess, a photoresist mask could beformed over the top surface of the first dielectric layer to expose theregion where the recess is to be formed. A selective etch that isselective between the first dielectric layer 406 (e.g., oxide) and thesource (e.g., silicon) can then be used to form the landing pad recess.As shown, the landing pad recess has a width w₁, and a depth h₁. Thewidth w₁ should be sufficiently large to allow proper alignment of a viaover a landing pad to be formed in the recess 500.

In FIG. 6, the contact holes and the landing pad recesses have beenfilled (and CMP performed) to form a first contact 600 and a secondcontact 602, where the second contact 602 has a landing pad 604 near thefop thereof. In one embodiment, the fill process could include multiplesteps, namely, forming a liner layer, and then depositing fill materialto fill the holes. The liner layer could be titanium (Ti) nitride (TiN),where a thin layer of titanium is usually first deposited after whichTiN is deposited to act as a barrier between the fill material and thesilicon. In one embodiment, after the liner layer has been formed,tungsten could be used to continuously fill the contact holes andlanding pad recesses. The tungsten could be deposited by chemical vapordeposition (CVD), atomic layer deposition (ALD), combinations of CVD andALD, or other suitable mechanisms. Because the gaseous CVD process canfill smaller geometries more easily than electroplating, the area of thelanding pad (e.g., which relates to width w₁) can be smaller than moreconventional landing pads where electroplated copper is used. In otherembodiments, other metals such as aluminum could be used for the fillmaterial for the contact holes and landing pad recesses.

FIG. 7 shows a structure after metal1 interconnect trenches 700 havebeen formed. Often, a series of etches may be used to form the metal1interconnect trenches 700. For example, one etch could etch the firstdielectric layer 406 and another could etch the fill material of thefirst contact 600. The metal1 interconnect trenches 700 have a width,w₂, and a height, h₂. The area associated with the metal1 interconnecttrenches 700 (which relates to width w2) is often greater than the areaassociated with the landing pad 604 (which relates to width w1.Therefore, the landing pad width w1 will often be larger than theinterconnect line width w2, but because the second dimension of theinterconnect line could be much larger than the second dimension of thelanding pad the area of the line is much larger than the area of the padso does not present a problem to the copper electroplating process.

In addition, the height h₂ could often be different from height h₁,although it could be approximately the same as height h₁. In otherun-illustrated embodiments, the dielectric layer 406 may be removed andthe fill material of the contact 600 may be left standing in the trenchrecess 700, consequently leaving a “pillar” of first contact material inthe trench.

In FIG. 8, copper or another material has been deposited or grown in themetal1 interconnect trench 700 to form a metal1 interconnect line 800.As previously mentioned, this metal1 interconnect line could carrysignals into the plane of the page between devices. This allowslow-resistivity copper (or other materials) to be used for the metal1interconnect lines.

One method for forming the copper is now discussed. First, a thin Cuseed layer is deposited using PVD. Cu electroplating is then performed.If the aspect ratio of the trench (depth/width) is high then the seedlayer thickness may get thin along the bottom edges of the trench. Ifthe seed layer is not continuous, then electroplating may fail. The seeddeposition thickness can be increased to counter this. However, as theseed layer thickness is increased, the opening near the top of thetrench may be pinched off. At some point, the opening will be too smallto allow the electroplating chemicals to enter and a void may occur.These problems can be solved by reducing the aspect ratio or by reducingthe trench depth. However, that comes with the penalty of higher sheetresistance.

More specifically, there are several types of voids that may occur. Onetype of void (seams) may occur if there is a long, wide trench which iseasy to fill. As its width is reduced, at some point the aspect ratiowill be such that the seed layer at the top will pinch the openingleading to a void lower down in the trench during the Cu electroplatingstep. This void will be like a cylindrical hole along the length of thetrench. During subsequent curing this void moves up and forms a seamrunning along the length of the trench. This happens to be a low energystate for the system. Often, these seams are undesirable but detectable,stable, and not a reliability problem. Another type of void (bubbles)may occur when a long, narrow trench has its length reduced. At somepoint when the length is almost as small as the width, the seed layerpinches the opening from all sides. This time the void in the Cu afterelectroplating is more like a bubble. During curing, this spherical voidmoves to the bottom of the bench, and may result in very thin Cu(perhaps even a gap) near the bottom of the trench. Thus, as the currentflows vertically from the contact into the landing pad or interconnectline, the current density is high and results in instability and gapformation. This may be a serious EFR and reliability problem. Therefore,even though narrow trenches are as difficult to fill they can beacceptable in the design as long as their length is above a criticalvalue so that a seam is formed instead of bubble-like voids at thebottom. In typical technology nodes, this may limit the minimum area ofa Cu landing pad.

In FIG. 9 a second dielectric layer 900 has been formed over the topsurface of the existing structure.

In FIG. 10, after photoresist has been patterned, via holes 1000 areformed in the second dielectric layer 900 so as to coincide with thelanding pads 604.

In FIG. 11, metal2 trenches or landing pad recesses 1100 are formed nearthe top of the via holes 1000.

In FIG. 12, the via holes and metal2 trenches and/or landing padrecesses are filled, often with copper. Therefore, vias 1200 and metal2interconnect lines and/or metal2 landing pads 1202 are formed. In someembodiments, upper layer landing pads could also be made with a reducedarea in a manner similar to that of the landing pads in metal1.Additional layers of interconnect (e.g., metal3, metal4, etc.) couldalso be fashioned in this manner.

Therefore, FIG. 13 shows a manufactured device 1300. This configurationprovides an excellent blend of cost and performance compared withpreviously discussed FIG. 1. The configuration still could providerelatively high performance because the metal1 interconnect line 800could be made of copper. Thus, there could be relatively low-resistancemetal1 interconnects between devices. Further, due the reduced area orwidth w₁ of the landing pad 604, the area of a standard cell may bereduced by an amount that relates to the number of landing pads in thestandard cell. Even if the landing pad 604 is made of tungsten, whichhas a relatively high resistivity, the performance degradation due tothe tungsten is relatively small because signals travel verticallyacross the landing pad 604 (i.e., from the contact 602 to the via 1200and vice versa), and not horizontally between devices.

In some embodiments, relatively long interconnect lines could be made ofcopper while other (relatively short) interconnect lines could be madeof tungsten. Thus, it will be appreciated that there are numerouscombinations of materials for interconnect lines and landing pads thatare encompassed by the present invention.

Referring now to FIG. 14 one can see another flowchart 1400 for forminglanding pads with a reduced area. FIG. 14's embodiment differs from FIG.3's embodiment in that in FIG. 14, the landing pads and metal1interconnect lines are formed concurrently and have the samecomposition. By contrast, in FIG. 3 the landing pads and metal1interconnect lines were formed in separate steps.

Referring now to FIGS. 15-21, one can see a several cross-sectionalviews during the manufacture of the device. These cross-sections are butone example of a method corresponding to the flowchart of FIG. 14, andother examples are also possible. For purposes of clarity andsimplicity, these cross sectional views do not explicitly show allblocks of the flowchart. For example, patterned resist layers (masks)are not shown, nor are CMP blocks.

Referring now to FIG. 15, one can see a structure 1500 in which firstand second contact holes 1502, 1504 have been formed in the firstdielectric layer 1506. For example, these contact holes 1502, 1504 couldbe formed by using suitable etches as discussed above.

In FIG. 16, a landing pad recess 1600 has been formed near the top ofthe second contact hole 1504, and a metal1 trench 1602 has been formednear the top of the first contact hole. As shown, the landing pad recesshas a width w₁, and a depth h₂. The width w₁ should be sufficientlylarge to allow proper alignment of a via over a landing pad to be formedin the landing pad recess 1600. The metal1 trench has a width w₂ and thedepth h₃.

In FIG. 17, the contact holes, landing pad recesses, and metal1 trencheshave been filled (and CMP performed) to form a first and second contacts(1700, 1702, respectively), landing pads 1704, and metal1 interconnectlines 1706, respectively. In one embodiment, these features may befilled continuously, for example with tungsten. In other embodiments,the filling of these features may include multiple steps. For example,in one embodiment, this step could include deposition of a contact linerfollowed by metal deposition as previously discussed. Although the useof tungsten for the interconnect lines 1706 may result in higherresistance interconnect between devices compared to FIG. 3's flowchart,this embodiment is a more streamlined process and is therefore morecost-effective to implement. Other fill materials, such as aluminum,could also be used.

In FIG. 18 a second dielectric layer 1800 has been formed over the topsurface of the existing structure.

In FIG. 19, after photoresist has been patterned, vias holes 1900 areformed in the second dielectric layer 1800 so as to coincide with thelanding pads 1704.

In FIG. 20, metal2 trenches or landing pads recesses 2000 are formednear the top of the vias holes 1900.

In FIG. 21, the via holes and metal2 trenches and/or landing padrecesses are filled, often with copper. Therefore, vias 2100 and/ormetal2 interconnect lines and metal2 landing pads 2102 are formed.Additional layers of interconnect (e.g., metal3, metal4, etc.) couldalso be fashioned in this manner.

Referring now to FIG. 22 one can see another flowchart 2200 for forminglanding pads with a reduced area. FIG. 22's embodiment is in some ways ablend of the previously discussed embodiments. The flowchart looks verysimilar to FIGS. 14-21, but includes some extra process steps which arein the boxed area 2246. For purposes of simplicity and clarity, only theextra processing steps are discussed below.

As shown in FIG. 26, after the contacts 2500, 2502, metal 1 interconnectlines 2504, and landing pads 2606 have been formed (see FIG. 25), thefill is removed from the metal1 interconnect lines to form a metal1trench 2600. To remove the fill material, a photoresist mask (or othermask) is used to cover the landing pad 2606. Often, the top of the firstdielectric layer will also be covered to expose only the interconnectline 2504. After the mask has been patterned, the interconnect line willbe removed to form the metal1 trench 2600 with a width w₂ and height h₄that may differ from height h₃.

In FIG. 27, the metal1 trenches are filled to make metal1 interconnectlines 2700. As with previous embodiments, the metal1 interconnect lines2700 can have a different composition from the metal1 landing pads 2506to achieve a balance between good performance and minimal area.

FIG. 32 and associated FIGS. 33-41 show another method 3200 inaccordance with aspects of the invention. Compared to previouslydiscussed methods, this method 3200 may be advantageous in that it mayprovide lower aspect ratios for the contact holes. More specifically,because this method uses a first and second layer of dielectric to formthe landing pads and metal1 interconnect lines, the first dielectriclayer can be thinner that those discussed in previous methods.Therefore, due to the lower aspect ratios, this method 3200 may providemore reliable yields because etches and fills will be more reliable. Asa tradeoff, however, this method 700 will require more masks andlithography steps than the methods previously discussed. Therefore, thismethod would likely be more expensive to implement.

In some embodiments, the blocks corresponding to FIGS. 38 and 39 couldbe skipped to limit the costs associated with this method. In thesenon-illustrated embodiments, the contacts, metal1 landing pads, andmetal 1 interconnect lines would all be continuously formed out of thesame material (e.g., W).

As shown in FIG. 33, contact holes are etched into a first layer ofdielectric as previously discussed.

In FIG. 34, fill material is formed within the contact holes to formcontacts. Typically, this could be a multi-step fill that includes aliner layer and formation of fill material.

In FIG. 35, a second layer of dielectric material is formed.

In FIG. 38, metal1 trenches and metal1 landing pad recesses are formedby a suitable etch process.

In FIG. 37, the metal1 trenches and metal1 landing pad recesses arefilled to form metal1 interconnect lines and metal1 landing pads. Forexample, tungsten could foe deposited to for these features.

In FIG. 38, the fill from the metal1 interconnect lines has been removedto form metal1 trenches. These trenches will often be the same depth ifthey were etched at the same time in FIG. 36. Typically when thetungsten is etched out, the trench depth does not change.

In FIG. 39, fill material, such as copper, is deposited or grown toreform the metal1 interconnect lines.

In some un-illustrated embodiments, the metal 1 trenches and metal 1landing pads could be formed by using separate etch and fill steps. Forexample, instead of the process flow shown in FIGS. 35-39 where themetal 1 trenches and landing pads are etched concurrently, the metal 1trenches could be etched in one step and then filled. Subsequently, thelanding pads could be etched, and then later filled.

In FIGS. 40-43, a third dielectric layer is formed and vias are formedtherein as previously discussed.

Although aspects of the present invention have been illustrated anddiscussed above with respect to a MOSFET semiconductor device, theseaspects are equally applicable to other semiconductor devices: includingbut not limited to: BJTs, diodes, FinFETS, or any other semiconductordevice. These other semiconductor devices will typically have suitableterminals. For example, the terminals of a BJT could include a base, acollector, and an emitter, while the terminals of a diode could includean anode and cathode. Other devices could include other suitableterminals.

It will be appreciated that, substrate and/or semiconductor body as usedherein may comprise any type of semiconductor body (e.g., silicon, SiGe,SOI) such as a semiconductor wafer and/or one or more die on a wafer, aswell as any other type of semiconductor and/or epitaxial layersassociated therewith. Also, while reference is made throughout thisdocument to exemplary structures in discussing aspects of methodologiesdescribed herein, those methodologies are not to be limited by thecorresponding structures presented. Rather, the methodologies (andstructures) are to be considered independent of one another and able tostand alone and be practiced without regard to any of the particularaspects depicted in the figures. Additionally, layers described herein,can be formed in any suitable manner, such as with spin on, sputtering,growth and/or deposition techniques, etc.

Also, equivalent alterations and/or modifications may occur to thoseskilled in the art based upon a reading and/or understanding of thespecification and annexed drawings. The disclosure herein includes allsuch modifications and alterations and is generally not intended to belimited thereby. In addition, while a particular feature or aspect mayhave been disclosed with respect to only one of several implementations,such feature or aspect may be combined with one or more other featuresand/or aspects of other implementations as may be desired. Furthermore,to the extent that the terms “includes”, “having”, “has”, “with”, and/orvariants thereof are used herein, such terms are intended to beinclusive in meaning—like “comprising.” Also, “exemplary” is merelymeant to mean an example, rather than the best. If is also to beappreciated that features, layers and/or elements depicted herein areillustrated with particular dimensions and/or orientations relative toone another for purposes of simplicity and ease of understanding, andthat the actual dimensions and/or orientations may differ substantiallyfrom that illustrated.

1. An integrated circuit that includes at least one semiconductordevice, comprising: a first contact associated with a first terminal ofthe semiconductor device, the first contact spanning a dielectric layerand coupling the first terminal to an interconnect line thatcommunicates signals horizontally on the integrated circuit, where theinterconnect line has a first composition; a second contact associatedwith a second terminal of the semiconductor device, the second contactspanning the dielectric layer and coupling the second terminal to alanding pad to which a via is coupled, where the landing pad has asecond composition that differs from the first composition.
 2. Theintegrated circuit of claim 1, where the interconnect line has a firstlateral area and the landing pad has a second lateral area that isdifferent from the first lateral area.
 3. The integrated circuit ofclaim 2, where the landing pad comprises tungsten.
 4. The integratedcircuit of claim 2, where the interconnect layer comprises copper. 5.The integrated circuit of claim 1, where the via includes a via-tophaving a third lateral area that is greater than the second lateral areaof the landing pad.
 6. The integrated circuit of claim 1, where thelanding pad has a first height that differs from a second heightassociated with the interconnect layer.
 7. The integrated circuit ofclaim 1, where the semiconductor device is a MOSFET, and the firstterminal and second terminals each comprise one of the following threeelements; a gate electrode, a source region, and a drain region.
 8. Amethod of forming an integrated circuit, comprising: forming first andsecond holes through a first dielectric layer; forming a landing padrecess near the top of the second hole; continuously filling the firsthole, second hole, and landing pad recess with a first fill material;removing a portion of the first dielectric layer from near the top ofthe first hole to form a trench; and filling the trench with a secondfill material that is different from the first fill material.
 9. Themethod of claim 8, where removing the portion of the first dielectriclayer further comprises: removing the first fill material from near thetop of the first hole to form the trench.
 10. The method of claim 8,where the trench has a first area and the landing pad recess has asecond area that differs from the first area.
 11. The method of claim 8,where continuously filling comprises: forming a liner layer; anddepositing the first fill material over the liner layer to at least thetop of the first hole, the second hole, and the landing pad recess. 12.The method of claim 8, where the first fill material comprises tungsten.13. The method of claim 8, where the second fill material comprisescopper.
 14. The method of claim 8, further comprising: forming a seconddielectric layer over the filled trench and filled landing pad recess;and forming a via hole in the second dielectric layer, where the viahole vertically coincides with the filled landing pad recess.
 15. Amethod of forming an integrated circuit, comprising: forming first andsecond contact holes through a first dielectric layer, the first andsecond contact holes associated with terminals of a semiconductordevice; forming a landing pad recess near the top of the second hole;forming a trench near the top of the first hole; and continuouslyfilling the first contact hole, the second contact hole, the landing padrecess, and the trench with a first fill material.
 16. The method ofclaim 15, further comprising: removing the first fill material from thetrench to form another trench; and filling the another trench with asecond fill material that is different from the first fill material. 17.The method of claim 15, further comprising: prior to continuouslyfilling, forming a liner layer in the first contact hole, the secondcontact hole, the landing pad recess, and the trench.
 18. A method offorming an integrated circuit, comprising: forming first and secondholes through a first dielectric layer; filling the first and secondholes with a first fill material; forming a second dielectric layer overthe first dielectric layer and filled first and second holes; forming atrench and a landing pad recess in the second dielectric layer, wherethe trench vertically coincides with the first hole and where thelanding pad recess vertically coincides with the second hole; fillingthe trench and the landing pad recess with the first fill material;removing first fill material from the trench to form another trench; andfilling the another trench with a second fill material that is differentfrom the first fill material.
 19. The method of claim 18, furthercomprising: leaving the first fill material in the landing pad recesswhile the first fill material is removed from the trench.
 20. The methodof claim 19, where the first fill material comprises tungsten and thesecond fill material comprises copper.
 21. The method of claim 20,further comprising; forming a third dielectric layer over the filledanother trench and filled landing pad recess; and forming a via hole inthe third dielectric layer, where the via hole vertically coincides withthe filled landing pad recess.
 22. The method of claim 18, where thetrench has a first area and the landing pad recess has a second areathat differs from the first area.
 23. An integrated circuit thatincludes at least one semiconductor device, comprising: a first contactassociated with a first terminal of the semiconductor device, the firstcontact spanning a dielectric layer and coupling the first terminal toan interconnect line that communicates signals horizontally on theintegrated circuit, where the interconnect Sine and first contact sharea first composition; a second contact associated with a second terminalof the semiconductor device, the second contact spanning the dielectriclayer and coupling the second terminal to a landing pad to which a viais coupled, where the landing pad and second contact share the firstcomposition.
 24. The integrated circuit of claim 23, where the firstcomposition comprises tungsten.
 25. The integrated circuit of claim 23,where first contact, interconnect line, second contact, and landing padare formed via a dual-damascene process.